1. Field of the Invention
The present invention relates to a semiconductor device and a data processing system including the same, and more particularly relates to a semiconductor device capable of reducing its power consumption in the standby state and a data processing system including the semiconductor device.
2. Description of Related Art
In recent years, an operation voltage of semiconductor devices is steadily reduced for reducing their power consumption. Some of currently available semiconductor devices have an operation voltage as low as 1 V. However, a threshold voltage of a transistor needs to be reduced following the reduction in the operation voltage, and this fact leads to a problem that a subthreshold current of the transistor in a non-conductive state is increased. As a solution to this problem, a power gating control method in which power lines are separated into main power lines and dummy power lines has been proposed in Japanese Patent Application Laid-open Nos. H05-347550, 2000-82950, and H08-227580.
In a semiconductor device disclosed in Japanese Patent Application Laid-open No. H05-347550, there is disclosed a technique in which all power nodes of a circuit block to be subjected to a power gating control are connected to dummy power lines. Furthermore, when the circuit block is in an active mode, the same voltage as that of the main power line is supplied to the circuit block by short circuiting the main power lines and the dummy power lines, and when the circuit block is in a standby mode, a lower voltage than that of the main power line is supplied to the circuit block by connecting the main power lines and the dummy power lines via a resistor. Consequently, in the active mode, a signal having a desired amplitude is transmitted through the circuit block, and because the voltage between a source and a drain of a transistor that is turned off is lower in the standby mode than in the active mode, a subthreshold current can be reduced.
However, in the semiconductor device disclosed in Japanese Patent Application Laid-open No. H05-347550, as shown in FIG. 11 thereof, a level converting circuit that amplifies an amplitude of an output signal is required at a later stage of the circuit block. This is because a level of the output signal in the standby mode differs from that in the active mode. If the output signal is not amplified, there is an increased leakage current in an input unit (an input initial stage) of the circuit block of the next stage that is not subjected to the power gating control. Assuming that an electric potential that indicates a high level in the active mode is VDD, and an electric potential that indicates a high level in the standby mode is VDDT (<VDD), if a threshold value of a P-channel MOS transistor that constitutes the input initial stage of the circuit block of the next stage that is not subjected to the power gating control is VDD−VDDT or less, the P-channel MOS transistor of the input initial stage, which needs to be turned off, is in fact turned on, and a through current disadvantageously flows. Therefore, in the semiconductor device disclosed in Japanese Patent Application Laid-open No. H05-347550, the level converting circuit needs to be connected at the later stage of the circuit block that is subjected to the power gating control. Thus, when there are several circuit blocks that are subjected to the power gating control and are not subjected to the power gating control, as many level converting circuits are required, leading to an increased circuit size. In addition, signal delays are caused due to the increased number of logical steps due to the level converting circuits.
Meanwhile, Japanese Patent Application Laid-open Nos. 2000-82950 and H08-227580 disclose a technique in which, among logic circuits constituting the circuit block that is subjected to power gating control, a power node on a high side is connected to a main power line and a power node on a low side is connected to a dummy power line for a logic circuit that needs to output a high level at the time of standby, and a power node on a high side is connected to a dummy power line and a power node on a low side is connected to a main power line for a logic circuit that needs to output a low level at the time of standby. According to this technique, because a source of a transistor that is turned off in a standby mode is invariably connected to a dummy power line, by disconnecting a dummy power line from a main power line at the time of standby, almost no subthreshold current flows of the transistor that is turned off.
However, in the semiconductor device disclosed in Japanese Patent Application Laid-open Nos. 2000-82950 and H08-227580, every power node of each logic circuit needs to be connected to either the main power line or the dummy power line according to a logic level fixed (static) at the time of standby. Consequently, the wiring structure becomes complex (requiring connecting each of the plurality of logic gates alternately to two different power lines (power nodes)). Furthermore, even when a slight alteration in a design (such as, an alteration of the number of stages of the logic gate) is required, there can be cases where connection destinations of the power nodes in several logic circuits have to be changed, making alterations in design a time-consuming task.